Novas Adds Timing Debug to Debussy
Debussy 5.1 Includes Numerous User-Requested Refinements
SAN JOSE, Calif.--(BUSINESS WIRE)--Nov. 26, 2001--Novas Software,
Inc., the leader in debug systems for complex chip designs, today
announced that it has added timing debug capabilities to its
Debussy® Debug System. These new capabilities are available as part
of the company's new version 5.1 release of Debussy. The new version
also includes other user-requested refinements, such as support for
additional operating systems and simulator integrations.
"Novas is committed to providing the industry's best debugging
solution to those who design and verify complex chips," said Scott
Sandler, president and CEO of Novas. "This newest release of Debussy
extends our users' ability to easily locate, isolate and understand
the causes of bugs in their SoC and other complex chip designs."
With the new timing analysis debug capabilities users can, for the
first time, annotate delays from a standard delay file (SDF) file into
a gate-level schematic. As a result, they can locate, isolate and
analyze the logic along timing paths within the same debug system they
use for simulation debug. Users gain the ability to rapidly visualize
longest and shortest logic paths, so they can quickly understand the
causes of timing problems. This yields engineering time and resource
gains because timing problems can be fixed more quickly and
accurately.
Sandler continued, "Users already familiar with the Debussy system
will enjoy this increased functionality. New users will find that the
ability to use one system across the full range of functional and
timing verification tools provides dramatic productivity improvements
to themselves as well as other members of their design team."
In addition to the timing debug capabilities, Debussy 5.1 includes
dozens of other enhancements to improve usability across the entire
system, including nTrace, nSchema, nState, and nWave. A few of the
upgrades included in Debussy 5.1 are:
- Support for the Extended VCD format, including the ability to
annotate signal direction in schematics
- Interactive mode support for the Cadence NC simulator on the
NT platform
- Interactive mode support for the Synopsys VCS simulator on the
Linux platform.
Pricing and Availability
Debussy 5.1 is available now. More information on its new
capabilities is available on Novas' web site at www.novas.com.
Current customers on active maintenance contracts can download the
software and obtain updated licenses for version 5.1 today at
www.novas.com. New customers should contact Novas to determine the
configuration that best suits their requirements.
About Novas
Novas Software, Inc. focuses on improving the human understanding
process involved in debugging IC and SoC designs. The company's
technology and products provide designers with the ability to shorten
verification and debug cycles--the most labor-intensive and expensive
portions of the design process. With its Debussy®, Verilog and VHDL
debug system, designers can easily locate, isolate, and understand the
causes of unexpected design behavior in half the time of traditional
solutions, thereby maximizing the efficiency of engineering resources,
significantly reducing costs and accelerating the process of getting
silicon to market. Novas has over 7,000 systems in use at hundreds of
customer sites worldwide. For more information visit www.novas.com or
send email to info@novas.com.
Novas Software and Debussy are registered trademarks of Novas
Software, Inc. All other trademarks are the property of their
respective owners.
Contact:
Novas Software
Lorie Bowlby, 408/467-7871
lorie@novas.com
or
KJ Communications
Kella Knack, 650/508-0371
kjcomk@cs.com
